When I first started this project there were a lot of terms I did not understand and several concepts that were completely new to me. Inorder to successfully hand build a retro computer, understanding a few key concepts is required. As this guide and the project moves forward items will be added to this page to help explain what exactly is going on and why with some of the choices that are made. This page may get very long but each topic will be found and contained under a dedicated heading.
What is the value of a wire that is not connected to 5v or GND?
If Logic Chip A Pin2 is wired directly to Logic Chip B Pin2. What is the value of Logic Chip B Pin2 if Logic Chip A is disabled or powered off?
What if you need Logic Chip B Pin2 to be ‘High’ when Logic Chip A is disabled?
The answer is Pull Resistors. Pull resitors are connected between the Logic Circuit and GND/Vcc to force a value when the signals are inactive.
Pull-UP resistors are connected between the Pin and the Positive voltage supply (Vcc). A Pull-UP resistor pulls the value of the wire up to the Voltage it is connected to causing the wire to become ‘High’ when all the other signals inactive.
Power supplies can be very noisey. Varations in voltages can cause a wide range of strange problems in our circuits. Bypass capacitors buffer the noise and the voltage drops by providing power that has built up in the capacitor to the circuits when there is irregularity. Bypass capacitors are very often left out of schematics with the assumption you know to add them. Most of the circuits in the 8085 project are going to be very simple but bypass capacitor may still be needed. Better safe than sorry.
Memory Address, Decoding, Layout
(This section will eventually be broken out into a individual page about memory access)
For a 8080/8085/Z80 the address bus is 16 wires connected to the A0-15 pins of the CPU. Each kind of memory that the CPU will access directly has to be connected (in parallel) to these 16 wires. This means that 2k of EPROM, 256bytes of ROM, and 32k of SRAM made up of 4 8k memory chips all have to be wired togheter with the same A0-15 wires. A memory chip only has the number of address pins needed to access all of the memory inside of the chip. Each address pin of the chip corrosponds to the same numbered address pin on the CPU. So CPU A0 goes to Memory A0, CPU A1 goes to Memory A1, CPU A16 goes to?? Wait a 2k chip doesn’t have an A16… Keep this in mind for the next paragraph on memory addressing.
Addresses are thought of as numeric values in hex, binary or decimal. The Address (0x0001) «0000 0000 0000 0001» when coding represents the Voltage values of the CPU pins A0-15 with value pin A0 is ‘High’ while A1-15 are ‘Low’. When a memory chip is hooked up to the address bus it takes the Voltage values of each pin and produces the data stored at that location inside of its internal circuits. Since in this case the address is 0x0001 ALL memory chips connected to A0-15 will respond with data stored at 0x0001.
- How does the CPU decide which chip is the one you wanted?
- What if one chip outputs 11110000 and another 00001111 does the CPU get 11111111?
- What about addresses that involve pins that the memory chips aren’t connected to?
- Chips that have 8 pins respond with the data at the first 8pins even when 10 are used by the CPU. How do we access all 64k available bytes?
The answer is Chip Enable and address decoding.
Memory Chip Enable
There is a pin on the chip called !CE (Or CE with a line over it) also known as Not-ChipEnable. This pin is used to control the output of the chip. When the pin voltage is ‘Low’ the chip will output data to the d0-7 lines. When the pin voltage is ‘High’ the chip will be inactive (remember if all the chips are inactive you need Pull Resistors). Connecting CE to a decoder will allow selection of the chip that should output.
Address decoding is the method used to combine small chips into larger array of memory. For example using 4 256byte chips to give the CPU 1024bytes total.
|1 1111 1111||511|
|10 1111 1111||755|
|11 1111 1111||1023|
This chart shows to address 256 bytes we need 8 address pins (0 counts as an address so everything is n-1). Each bit in the binary address is a pin on the chip. This means CPU A0-A7 (8pins) should be wired directly to the each chip’s 8 pins.
To aceess a total of 1024bytes 10 address pins are required. Each 256byte memory chip has only 8 pins. Of the 10 pins required to address 1024bytes 2 are free and not connected to memory chips allowing pin8 and pin9 for special purpose. Thats right Chip Select!
Taking bits 8 and 9 in the table above we can make a truth table that shows how to turn off/on the chips to give the CPU access to all 1024bytes.
This chart shows that using 2 pins will give us the ability to select between 4 chips. Using this info we can now decode each address and figure out which chip and which byte will be given to the CPU. Some examples:
- 10 0000 0100: ChipC address 4 but the CPU thinks it is asking for byte 516!
- 11 0001 0001: ChipD address 17 but the CPU thinks it is asking for byte 785!
- 00 0000 1000: ChipA address 8 and the CPU thinks it is asking for byte 8!
- 00 1000 0001: ChipA address 129 and the CPU thinks it is asking for byte 129!
- 11 0000 0000: ChipD address 0 and the CPU thinks it is asking for byte 768!
What happens when the CPU tries to access an address that has more than 10 bits?
- 0100 0000 0100: ChipA address 4 and the CPU thinks it is asking for byte 1028!!!
Since there are no chips wired to address pin10 A9,A8 is 00 which turns on ChipA. The software running on the CPU thinks that it is accessing byte 1028 but it is actually accessing byte 4. In a modern PC the software running on the machine (Operating System) would prevent this siutation because it would be configured only to allow access to the configured size. This is a great segway into the next topic though, Memory Layout.
Following the address decoding methods exposes some shortcomings in flexibility about what size and type of memories can be combined and used together. In the Address Decoding section all 4 chips were of equal size which allowed a very simple and easy method of chip select. Lets walk through a problem before defining memory layout rules.
What if ChipB from the Address Decoding section was 2048byte not 256byte? Would this allow access to 2816bytes (256+2048+256+256)?
|1 1111 1111||511|
|10 1111 1111||755|
|11 1111 1111||1023|
|111 1111 1111||2047|
The short answer is No.
As in this chart a 2048byte chip requires 11-pins. The CPU has 16-pins A0-A15 so obviously we can just wire A0-A10 to the memory chip. However, like in the Gotcha’s section for address 0100 0000 01000, if bits 9,8 are 00 ChipB is disabled. So even if ChipB had all 11-pins wired to the CPU A0-A10 ChipB would be turned off and wouldn’t respond so the requested address.
What if we wire ChipB CE to pin10 directly that way when pin10 is active ChipB is on? Well, that would be true but since pin9,8 are 00 ChipA is also ON and there is no way to turn it off.
These problems introduce a few memory layout rules that if you were a kid like me in the 80’s and 90’s didn’t make much sense but sure do now. These rules can be worked around with very complex circuitry but the level of effort and danger of mistakes is very high. The industry sort of settled on these rules to reduce complexity and cost and the rules still apply even today in modern computing.
- Memory chips should all be the same size.
- Memory chips that are larger than others will have the extra space inaccessible.
- Memory chips smaller than others will cause gaps in addresses that the software needs to be aware of.
- The decoder makes address pins that are higher than the position of the decoder inaccessible.
Example Layouts for a 16-bit address CPU (Z80, 8080, 8085)
|1 to 2||1k ROM, 1k RAM||2k||Good Layout|
|1 to 2||1k ROM, 32k RAM||2k||Bad, leaves 31k gap between the 1k and start of 32k|
|1 to 2||32k ROM, 32k RAM||64k||Good Layout|
|2 to 4||2k ROM, 3x 2k RAM||8k||Good Layout|
|2 to 4||16k ROM, 3x 16K RAM||64k||Good Layout|
|2 to 4||16k ROM, 3x 2K RAM||64k||Bad, Leaves 14k gaps between each RAM chip|
|3 to 8||2k ROM, 7x 2k RAM||16k||Good Layout|
|3 to 8||8k ROM, 7x 8k RAM||64k||Good Layout|
|3 to 8||16k ROM, 7x 16k RAM||64k||Suboptimal, wastes 8k of each chip|
|4 to 16||4x 2kROM, 12x 2k RAM||32k||Suboptimal, very complex wiring|